//====================================================================================
//    COPYRIGHT(C) Innobeam
//    ALL RIGHTS RESERVED
//====================================================================================
//Filename    : lan9252_ini.v rev 1.0
//Created On  : 20170902
//Author      : shilong.zhang
//Description :	read lan9252 REG 64h for lan9252 initial
//Include     : 
//Modification: 
//====================================================================================
module lan9252_ini
(
	iClk	,//input clock
	iRst_n	,//reset active low

	ivData	,//32bit input data from lan9252_interface module
	iDone	,//input done signal from lan9252_interface module
	ovAddr	,//output 16bit address to lan9252_interface module
	oRdEn	,//output read enable to lan9252_interface module
	oReady	 //output signal,active high,LAN9252 chip is ready.
);
//====================================================================================
//    parameter
//====================================================================================
parameter ADDR = 16'h0032;

//====================================================================================
//    port
//====================================================================================
input 			iClk;
input			iRst_n;

input			iDone; //read or write LAN9252 reg complete signal
input	[31:0]	ivData;
output	[15:0]	ovAddr;
output			oRdEn;
output			oReady;

//====================================================================================
//    signal
//====================================================================================
reg				rReady;	//ready signal output
reg				rRdEn;	//read enable signal
reg		[31:0]	rvData; //data reg to store read data;
reg				rDone;	//
reg				rRdFlag; //(rRdFlag==1) indicats that should sent read enable signal
reg		[3:0]	rvCnt;  //counter

//====================================================================================
//    module body
//====================================================================================

assign oReady = rReady;
assign oRdEn = rRdEn;
assign ovAddr = ADDR;

// store read input data when (Done == 1)
always @ (posedge iClk or negedge iRst_n) begin
	if (iRst_n == 1'b0) begin
		rvData <= 32'h0000_0000;
		rDone <= 1'b0;
		end
	else begin
		if (iDone == 1'b1) begin
			rvData <= ivData;
			rDone <= 1'b1;
			end
		else begin
			rvData <= rvData;
			rDone <= 1'b0;
			end
		end
	end

// continue to read 64h address of LAN9252 when (Ready == 0)
// change Ready to 1,when (data read in == 32'h8765_4321),then stop reading 64h
always @ (posedge iClk or negedge iRst_n) begin
	if (iRst_n == 1'b0) begin
		rReady <= 1'b0;
		rRdEn <= 1'b0;
		rRdFlag <= 1'b1;
		rvCnt <= 4'd0;
		end
	else begin
		if (rReady == 1'b0) begin
			if (rRdFlag == 1'b1) begin
				rRdEn <= 1'b1;
				rRdFlag <= 1'b0;
				rReady <= 1'b0;
				rvCnt <= 4'd0;
				end
			else begin
				if (rDone == 1'b1) begin
					if (rvData == 32'h8765_4321) begin
						rReady <= 1'b1;
						rRdEn <= 1'b0;
						rRdFlag <= 1'b0;
						rvCnt <= 4'd0;
						end
					else begin
						rReady <= 1'b0;
						rRdEn <= 1'b0;
						rRdFlag <= 1'b1;
						rvCnt <= 4'd0;
						end
					end
				else begin
					rReady <= 1'b0;
					rRdEn <= 1'b0;
					rvCnt <= rvCnt + 1'b1;
					if (rvCnt == 4'hF) begin
						rRdFlag <= 1'b1;
						end
					else begin
						rRdFlag <= 1'b0;
						end
					end
				end
			end
		else begin
			rReady <= 1'b1;
			rRdEn <= 1'b0;
			rRdFlag <= 1'b0;
			rvCnt <= 4'd0;
			end
		end
	end

endmodule
